Many portable products, such as mobile phones, laptop computers, personal data assistants (PDAs) or the like, utilize a processor executing programs, such as, communication and multimedia programs. The processing system for such products includes a processor complex for processing instructions and data. The functional complexity of such portable products, other personal computers, and the like, require high performance processors and memory. At the same time, portable products have limited energy sources in the form of batteries and provide high performance operation at reduced power levels to increase battery life. Many personal computers being developed today also are being designed to provide high performance at low power drain to reduce overall energy consumption.
In order to guarantee correct operation and consistency of memory usage, a processor complex commonly enforces an ordering of operations on the use of memory which is shared by multiple processors, multiple program threads, multiple direct memory access (DMA) devices, or more generally by multiple bus masters. To control memory usage between multiple bus masters, a producer/consumer relationship may be defined between two or more processors or masters. In such a relationship, one processor or master that is writing data, or a “payload”, to shared memory is referred to as the producer. The other processor or master that is to receive or operate on the written payload is referred to as the consumer. The payload may be a single data item or more complex, such as multiple information packets or frames of data, for example.
To maintain order between the multiple bus masters, a consumer may not access the payload until notified by the producer that the payload may be safely accessed. Such notification may occur by means of a software/hardware interrupt, a semaphore update, or a register write setting an access indication bit or bits. The consumer bus master may then safely begin reading the payload information just written and perform its processing of the payload. When the consumer has completed its processing, it may write a modified payload back to memory and, in the process, become a producer of the modified payload.
At the point a consumer is ready to read another payload from memory, it notifies the producer of its readiness to process a new payload via a software/hardware interrupt, semaphore update, or register write, for example. This ordered sequence can continue indefinitely. In this producer/consumer relationship it is important for an entire payload to be completely written to memory prior to signaling the consumer that it is available to be accessed. If the consumer is signaled before this occurs, the consumer may actually read “stale” payload data, or data from a preceding payload. Because of write buffering in interconnect arrangements and any bridging to memory, write data could be stored and present in intermediate stages even though the producer has a write completion indication on its master interface as received from a first buffer in the interconnect arrangement. Synchronization of bus transactions is not maintained in such a situation.